Puslaidininkių projektavimo ir simuliavimo palaikymas per „ChipsC2-LT“ prieigos mazgą.
This service is delivered by VILNIUS TECH.
Design and Modelling
Technical Scope and Capabilities
Ši paslauga teikia pagalbą vartotojams viso puslaidininkių projektavimo ciklo metu - nuo koncepcijos apibrėžimo bei galimybių analizės iki projektavimo, simuliavimo, pasirengimo gamybai („tape-out“) ir verifikavimo. Paslauga teikiama koordinuojant veiksmus su ES puslaidininkių projektavimo platforma (EU Chips Design Platform), kuri suteikia prieigą prie elektronikos projektavimo automatizavimo (EDA) įrankių, gamybos proceso projektavimo rinkinių (PDK), intelektinės nuosavybės (IP) bibliotekų bei gamybos kelių.
The service supports users in
If the required expertise is not available at VILNIUS TECH, users are guided to an appropriate partner or resource within the EU Chips Design Platform.
- concept and technical challenge definition
- feasibility analysis and system-level definition
- access to design tools, PDKs and simulation environments through the EU Chips Design Platform and associated infrastructures such as Europractice
- design, modelling and verification
- MPW submission and fabrication coordination through platform channels
- post-silicon validation and testing.
Core Infrastructure / Tools / Equipment
The service uses and facilitates access to
- Cadence
- ADS
- TCAD
- Europractice
- EDA tools
- PDKs
- IP libraries
- RF/DC testing infrastructure up to 26 GHz.
Service Delivery Mode
The service is delivered through
- engineering support
- feasibility analysis
- design and modelling support
- platform-access guidance
- tape-out preparation support
- post-silicon validation support.
Expected Outputs
The stated outputs include
- schematics
- layouts
- simulation reports
- GDSII files
- tape-out packages
- measurement reports
- trained engineers.
Service Delivery Terms and Times
Design and testing activities are carried out under formally established Non-Disclosure Agreements. Where additional stakeholders are involved, such as chip design tool providers, technology platform operators or semiconductor manufacturers, tripartite or multi-party Non-Disclosure Agreements may be concluded.