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Access to cutting-edge semiconductor R&D facilities across four Lithuanian institutions (FTMC, VU, VGTU, KTU), including ISO 5-7 clean rooms, MBE/CVD systems, e-beam lithography, laser processing systems, and advanced characterisation tools.
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Pilot lines
The Chips for Europe Initiative aims to expand and upgrade existing pilot lines, creating a robust infrastructure capable of advancing cutting-edge semiconductor technologies to higher maturity levels. These facilities will enable faster industrial adoption and commercial deployment of next-generation solutions.
The pilot lines will offer a unique environment for testing, experimentation, and validation of prototype systems that integrate breakthrough innovations (such as quantum technologies, artificial intelligence, and neuromorphic computing) as well as enhanced functionalities like security, energy efficiency, and integrated photonics.
By enabling real-time feedback from prototyping to design teams, these lines will allow engineers to refine and optimise design models before manufacturing, significantly shortening development cycles and reducing time-to-market.
All pilot lines will be accessible to stakeholders across the value chain on open and non-discriminatory terms. As world-class European assets, they will reinforce Europe’s position as a key player in global semiconductor innovation and provide a strong foundation for enhanced international collaboration.
The NanoIC Pilot Line, coordinated by IMEC, is dedicated to pushing the boundaries of semiconductor innovation beyond the 2 nm technology node. As a key European infrastructure, it supports the advanced development and pre-manufacturing of next-generation integrated circuits, reinforcing Europe’s strategic position in the global semiconductor landscape.
This pilot line accelerates R&D in nanometer-scale circuit technologies, directly addressing the challenges and demands of industry stakeholders. It plays a crucial role in supporting the European Union’s ambition to remain competitive in high-performance, energy-efficient, and scalable chip design and fabrication.
The NanoIC Pilot Line operates as an open innovation platform, bringing together academic institutions, industrial partners, and research organisations. It facilitates the co-development, validation, and commercialisation of emerging technologies, while ensuring broad access under fair and non-discriminatory conditions.
The APECS Pilot Line, coordinated by Fraunhofer (Germany), focuses on the development of advanced packaging and heterogeneous integration technologies that bring together diverse semiconductor materials, components, and functionalities within a single compact system.
As traditional monolithic scaling (Moore’s Law) reaches its physical and economic limits, heterogeneous integration becomes essential to meet the demands of next-generation systems.
APECS leverages technologies such as System-in-Package (SiP), 2.5D and 3D integration, enabling the combination of digital, analog, RF, memory, and photonic elements in highly efficient and flexible architectures.
This pilot line supports the European semiconductor ecosystem by accelerating the path from research to industrial manufacturing, in line with the objectives of the Chips Joint Undertaking.
The FAMES Pilot Line, coordinated by CEA-Leti (France), is part of the Chips for Europe Initiative and focuses on advanced semiconductor technologies for analog, mixed-signal, and power electronics applications, key enablers of next-generation connected and intelligent systems.
At its core, the pilot line builds on Fully Depleted Silicon On Insulator (FDSOI) technology, which enables the development of high-performance, low-power, and cost-efficient circuits. FDSOI is particularly suited for edge computing, automotive systems, IoT, and secure electronics.
FAMES provides a pathway to industrialise innovative designs, bridging the gap between R&D and large-scale manufacturing. It plays a vital role in strengthening Europe’s technological sovereignty by offering a robust platform for developing and validating advanced components under open and non-discriminatory access.
PIXEurope is the fifth Pilot Line initiative launched through the European Chips Joint Undertaking, established under the European Chips Act, to accelerate the development of photonic integrated circuit (PIC) technology – a critical enabler for high-speed computing, communications, quantum information systems, and beyond.
It will be Europe’s first fully integrated, distributed Pilot Line connecting the entire PIC value chain – from design and fabrication to integration, packaging, and testing – across multiple coordinated European sites within a unified and standardized framework.
With a budget of €400 million and the participation of 20 institutions from 11 European countries (Austria, Belgium, Finland, France, Ireland, Italy, Poland, Portugal, Spain, the Netherlands and the United Kingdom), PIXEurope will master key technology platforms spanning a broad range of materials – from silicon and silicon nitride to indium phosphide, lithium niobate, and beyond – while also supporting hybrid integration and the co-integration of photonic and electronic chips.
Through prototyping services, including Multi-Project Wafer runs, as well as access to advanced equipment and infrastructure, collaborative R&D projects, training and consultancy, the Pilot Line will serve companies of all sizes through a centralized open-access gateway.
The WBG Pilot Line, based in Catania (Italy) and developed in collaboration with Tampere University (Finland), is one of Europe’s key initiatives for advancing wide bandgap (WBG) semiconductor technologies. It focuses on the development, integration, and packaging of new high-performance, durable, and energy-efficient materials for next-generation power and RF applications.
Tampere University plays a leading role in the development and testing of WBG devices, including their integration into hybrid System-in-Package (SiP) architectures. This enables the creation of compact and robust solutions for demanding environments.
The pilot line supports the industrialisation of WBG materials and components for applications such as:
Electric motor controllers
Battery management systems
Solar inverters
5G network base stations
In parallel, advanced techniques for SiP fabrication are being developed to enable full system integration, a crucial step toward reinforcing Europe’s competitiveness and sustainability in the global semiconductor market.</p
Access to Infrastructure
The Lithuanian Chips Competence Centre (ChipsC2-LT) provides unified access to a network of cutting-edge semiconductor R&D facilities across four leading national institutions – FTMC, VU, VGTU, and KTU.
Facilities include high-grade ISO 5-7 clean rooms, molecular beam epitaxy (MBE) and chemical vapor deposition (CVD) systems, electron-beam lithography, laser processing systems, and advanced characterization tools.
Atomic layer deposition (ALD) is a thin-film deposition technique that builds materials one atomic layer at a time through sequential, self-limiting surface reactions. This precise process enables uniform coatings on complex surfaces and supports key advances in electronics, energy technologies, and advanced materials.
Oxygen plasma cleaning is a plasma-based surface treatment that effectively removes organic contaminants using reactive oxygen species, improving surface cleanliness and wettability without damaging the substrate. It is widely used in micro- and nanofabrication to enhance adhesion or clean samples prior to processes such as deposition or lithography.
Plasma-Enhanced Chemical Vapor Deposition (PECVD) is a versatile thin-film deposition technique that uses plasma to enable low-temperature growth of high-quality dielectric and semiconductor films.
Dry etching is a plasma-based process that delivers precise, directional material removal through RF-activated reactive gases, offering superior control compared to wet etching. It is ideally suited for high–precision micro- and nano-fabrication.
Lithography is a micro- and nano- fabrication process used to create precise patterns on various substrates. Combined with etching or lift-off process it enables the fabrication of features like trenches, vias, and metal layers. The Lithuanian Chips Competence Centre (ChipsC2-LT) offers three primary lithography techniques through its partner institutions.
Epitaxial growth is a semiconductor fabrication technique used to grow highly ordered crystalline layers on a substrate with precise control over thickness, composition, and material quality. These properties are critical for the performance of microelectronic, power, and optoelectronic devices.
Among the main methods, liquid-phase, vapor-phase, and molecular beam epitaxy (MBE), MBE is particularly important for research and advanced device development. It enables atomic-level control of growth under ultra-high vacuum, making it ideal for complex heterostructures and quantum-scale architectures that drive innovation in next-generation semiconductor devices.