Verification and Design Flow of Digital and Mixed-signal Chips

Learn to design, simulate and verify complex chip systems with top experts from Lithuania’s semiconductor ecosystem.
  • Vilnius, Lithuania
  • 8 weeks
  • English / Lithuanian

About the course

Who delivers the course

In this course, instructors from FTMC and several companies in the semiconductor industry will introduce you to the “why” and “what” of the digital chip design flow. You will learn about digital and mixed-signal simulation and verification techniques used in real industrial environments.

The course combines theoretical sessions with hands-on lab-based training, and will be organised on-campus in Vilnius.

Instructors and tutors in the course come from the following organisations: FTMC, VGTU, KTU, as well as industrial partners from the Lithuanian semiconductor ecosystem.

Training course Verification and design flow of digital and mixed-signal chips Chipsc2.lt

Academic coordinator of the course:

Dr. Gediminas

Course coordination:

Dr. Saulius

What you'll learn

  • A deep understanding of the design flow for ASICs and SoCs
  • Practical skills in RTL simulation, verification methodologies, and formal property checking
  • Insights into mixed-signal simulation and UVM-based testbenching
  • Exposure to Lithuanian infrastructure and labs, with access to ChipsC²-LT tools and services

Target group and objectives

This course is intended for a broad technical audience. Participants must hold a Master’s degree in a technical field (e.g., electronics, computer engineering, microelectronics), or demonstrate equivalent experience through relevant professional practice.

Applications will be assessed by the academic coordinator based on the submitted application form.

Required background knowledge:

  • Basics of digital circuits
  • Understanding of, and experience with, any hardware description language (VHDL, Verilog, or SystemVerilog)
  • Linux computer literacy

Upon completion of this course, the student will be able to:

🔸 Understand the relationship between design and verification:

  • Close integration between digital logic design and verification in SoC workflows

🔸 Apply multiple methods for verifying digital designs:

  • Linting / Code Review
  • Clock Domain Crossing (CDC)
  • RTL / Netlist Simulation
  • Emulation
  • Formal Property Verification (FPV)

🔸 Use industry-standard robustness techniques across the ASIC design pipeline:

  • Formal Verification
  • Static Timing Analysis (STA)
  • Back-end checks: Crosstalk, IR drop, Layout vs Schematic (LVS), Design rule checks

🔸 Design and debug verification testbenches:

  • Visual waveform inspection
  • Golden reference model comparisons
  • Inverse model testing (e.g., TX–RX)
  • Direct vs randomized testing
  • Assertion-based verification
  • Coverage analysis (code, functional, cover points)
  • Debugging from testbench outputs

🔸 Create and modify advanced verification environments:

  • Design, implement, and adapt UVM (Universal Verification Methodology) testbenches

🔸 Simulate and validate analog-mixed signal designs:

  • Understand digital vs analog simulators
  • Manage requirements and test runs
  • Develop a complete mixed-signal chip from concept to tapeout

🔸 Verify full SoC designs:

  • Perform software verification within SoCs
  • Work across multiple abstraction levels via behavioural modelling

🔸 Apply acquired knowledge in practical sessions:

  • Engage in hands-on workshops using industry-grade tools and ChipsC²-LT infrastructure

Program

This course is organised over 8 weeks, with one full-day session every Thursday.
Participants will follow a structured learning path combining theoretical modules and hands-on workshops.
The evaluation will take place on December 18, 2025. Participation to the evaluation is not mandatory.
This opening session introduces participants to the overall structure of a modern digital chip design process. It explains the motivations behind each stage and the real-world challenges of translating system requirements into silicon. Participants will gain insights into key terminology and the reasons behind the complexity of SoC design.

Schedule:

  • 09:00 – 09:30: Welcome & Introduction

  • 09:30 – 11:00: Module 1 – Overview of ASIC and SoC design flow

  • 11:00 – 11:30: Coffee break

  • 11:30 – 13:00: Module 2 – Chip lifecycle: from idea to fabrication

  • 13:00 – 14:00: Lunch

  • 14:00 – 15:30: Module 3 – Specification, architecture & RTL

  • 15:30 – 16:00: Coffee break

  • 16:00 – 17:00: Q&A and hands-on lab setup

In this session, participants continue exploring the digital design flow and begin hands-on work with simulation environments. The focus is placed on the need for early and continuous verification, illustrated through practical workshops.

Schedule:

  • 09:00 – 09:15: Welcome & setup

  • 09:15 – 10:45: Module 4 – Hands-on workshop 1: basic RTL design

  • 10:45 – 11:00: Coffee break

  • 11:00 – 12:30: Module 5 – Functional simulation with testbenches

  • 12:30 – 13:30: Lunch

  • 13:30 – 15:00: Module 6 – Debugging techniques & waveform analysis

  • 15:00 – 15:15: Coffee break

  • 15:15 – 17:00: Module 7 – Verification tools and best practices

This session explores various techniques used to ensure functional correctness throughout the digital design process. You’ll be introduced to static verification tools, linting, and Clock Domain Crossing (CDC) analysis. A practical lab will show you how to apply these methods in a standard ASIC toolchain.

Schedule:

  • 09:00 – 10:30: Functional verification methodology

  • 10:30 – 11:00: Coffee break

  • 11:00 – 12:30: Linting and CDC analysis techniques

  • 12:30 – 13:30: Lunch

  • 13:30 – 15:00: Lab – Setting up a tool-based verification flow

  • 15:00 – 15:30: Coffee break

  • 15:30 – 17:00: Debugging and best practices

This day focuses on how to build efficient and reusable testbenches. Participants will learn about directed and randomized testing, assertion-based verification, and coverage analysis. A hands-on lab will allow them to create a basic UVM-style simulation environment.

Schedule:

  • 09:00 – 10:30: Testbench architectures: styles and best practices

  • 10:30 – 11:00: Coffee break

  • 11:00 – 12:30: Simulation platforms and waveform analysis

  • 12:30 – 13:30: Lunch

  • 13:30 – 15:00: Lab – Building a functional testbench

  • 15:00 – 15:30: Coffee break

  • 15:30 – 17:00: Coverage and assertion debugging

This session introduces participants to verification techniques adapted to AI-oriented digital designs. You will learn how to validate custom accelerators and apply formal methods in the context of high-complexity architectures. A practical lab will demonstrate how to verify AI-focused RTL blocks.

Schedule:

  • 09:00 – 10:30: AI accelerator design flow and constraints

  • 10:30 – 11:00: Coffee break

  • 11:00 – 12:30: Formal methods and equivalence checking

  • 12:30 – 13:30: Lunch

  • 13:30 – 15:00: Lab – Verification of a digital AI architecture

  • 15:00 – 15:30: Coffee break

  • 15:30 – 17:00: Debug walkthrough and case study discussion

In this session, you will explore how analog and digital domains interact within chip design. You’ll learn how to simulate mixed-signal circuits using hybrid solvers, and how to debug interface-level issues. A lab session will guide you through verifying a basic analog-digital system.

Schedule:

  • 09:00 – 10:30: Introduction to mixed-signal design flows

  • 10:30 – 11:00: Coffee break

  • 11:00 – 12:30: Analog vs digital simulation engines

  • 12:30 – 13:30: Lunch

  • 13:30 – 15:00: Lab – Verifying analog-digital interactions

  • 15:00 – 15:30: Coffee break

  • 15:30 – 17:00: Debugging analog/digital boundary behaviours

This day focuses on modelling techniques and abstraction layers for mixed-signal verification. You’ll learn how to use behavioural models to speed up simulation, structure analog testbenches, and manage system-level complexity.

Schedule:

  • 09:00 – 10:30: Abstraction strategies in mixed-signal verification

  • 10:30 – 11:00: Coffee break

  • 11:00 – 12:30: Creating and modifying behavioural models

  • 12:30 – 13:30: Lunch

  • 13:30 – 15:00: Lab – Modelling analog/digital test environments

  • 15:00 – 15:30: Coffee break

  • 15:30 – 17:00: Reusability and simulation coverage analysis

In the final session, you’ll work on full-system verification including software components. You’ll explore how to test embedded software in SoCs, use verification layers from block to system level, and perform final simulations of mixed-signal systems.

Schedule:

  • 09:00 – 10:30: SoC-level verification approaches

  • 10:30 – 11:00: Coffee break

  • 11:00 – 12:30: Embedded software verification strategies

  • 12:30 – 13:30: Lunch

  • 13:30 – 15:00: Lab – Final system simulation

  • 15:00 – 15:30: Coffee break

  • 15:30 – 17:00: Summary, open questions & evaluation preparation

An optional evaluation will be held on December 18, 2025.

  • Students who attend all sessions will receive a Certificate of Attendance.

  • Those who complete the evaluation and meet the requirements will be awarded a Micro-Credential Certificate issued by FTMC and its academic partners.

Evaluation format includes a short-written assignment and a simulation-based practical test. No prior registration is needed, but attendance is required.

Practical information

Course schedule

Sessions are taught in English / Lithuanian and take place on Thursdays from 09:00 to 17:00.

Location

On campus, FTMC – Vilnius (Lithuania)
Saulėtekio al. 3, Vilnius

Registration

The regular registration fee is €480.
The fee includes: participation in all sessions, access to lab equipment and EDA tools, digital course materials, and on-site catering.
Participants will also receive a ChipsC²-LT learner access card for the duration of the course.

Eligible Lithuanian companies can benefit from partial reimbursement under national or EU support schemes.

Student & early-career discounts

  • PhD students, postdocs, and young graduates may apply for a reduced fee of €120 (application required and subject to approval)

  • Bachelor and Master students may apply for a reduced fee of €50 (application required and subject to approval)

  • Applications will be reviewed based on academic motivation and availability

Apply here

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